April 2020 ES0340 Rev 16 1/50
1
STM32F10xxC/D/E
Errata sheet
STM32F101xC/D/E and STM32F103xC/D/E
high-density device limitations
Silicon identification
This errata sheet applies to the revisions Z, Y, 1, 2, 3 and X of the STMicroelectronics
STM32F101xC/D/E access line and STM32F103xC/D/E performance line high-density
products. These families feature an Arm®32-bit Cortex®-M3 core, for which an errata notice
is also available (see Section 1 for details).
The full list of part numbers is shown in Table 2. The products are identifiable as shown in
Table 1:
by the revision code marked below the order code on the device package
by the last three digits of the internal order code printed on the box label
Table 1. Device Identification(1)
1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the
STM32F10xxC/D/E reference manual for details on how to find the revision code).
Order code Revision code(2) marked on device
2. Refer to Appendix A: Revision code on device marking for details on how to identify the Revision code on
the different packages.
STM32F103xC, STM32F103xD, STM32F103xE “Z”, “Y” or “1” or “2” or “3” or “X”
STM32F101xC, STM32F101xD, STM32F101xE “Z”, “Y” or “1” or “2” or “3” or “X”
Table 2. Device summary
References Part numbers
STM32F10xxC/D/E
STM32F101xC/D/E
STM32F101RC, STM32F101VC, STM32F101ZC
STM32F101RD, STM32F101VD, STM32F101ZD
STM32F101RE, STM32F101VE, STM32F101ZE
STM32F103xC/D/E
STM32F103RC, STM32F103VC, STM32F103ZC
STM32F103RD, STM32F103VD, STM32F103ZD
STM32F103RE, STM32F103VE, STM32F103ZE
www.st.com
Contents STM32F101xC/D/E STM32F103xC/D/E
2/50 ES0340 Rev 16
Contents
1Arm
®32-bit Cortex®-M3 limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Cortex-M3 limitations description for STM32F10xxC/D/E
high-density devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.1 Cortex-M3 LDRD with base in list may result in incorrect base register
when interrupted or faulted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.2 Cortex-M3 event register is not set by interrupts and debug . . . . . . . . . . 8
1.1.3 Cortex-M3 BKPT in debug monitor mode can cause DFSR mismatch . . 8
1.1.4 Cortex-M3 may freeze for SLEEPONEXIT single instruction ISR . . . . . . 9
1.1.5 Interrupted loads to SP can cause erroneous behavior . . . . . . . . . . . . . . 9
1.1.6 SVC and BusFault/MemManage may occur out of order . . . . . . . . . . . 10
2 STM32F10xxC/D/E silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Voltage glitch on ADC input 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Flash memory read after WFI/WFE instruction . . . . . . . . . . . . . . . . . . . . 14
2.3 Debug registers cannot be read by user software . . . . . . . . . . . . . . . . . . 14
2.4 Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . . . 15
2.5 Debugging Stop mode with WFE entry . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 Wakeup sequence from Standby mode when using more
than one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7 LSE start-up in harsh environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8 RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.9.1 USART1_RTS and CAN_TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.9.2 SPI1 in slave mode and USART2 in synchronous mode . . . . . . . . . . . . 18
2.9.3 SPI1 in master mode and USART2 in synchronous mode . . . . . . . . . . 18
2.9.4 SPI2 in slave mode and USART3 in synchronous mode . . . . . . . . . . . . 19
2.9.5 SPI2 in master mode and USART3 in synchronous mode . . . . . . . . . . 19
2.9.6 SDIO with TIM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.9.7 SDIO and TIM3_REMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.9.8 SDIO with USART3 remapped and UART4 . . . . . . . . . . . . . . . . . . . . . . 20
2.9.9 FSMC with I2C1 and TIM4_CH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.9.10 FSMC with USART2 remapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.9.11 FSMC with USART3 and TIM1 remapped . . . . . . . . . . . . . . . . . . . . . . . 21
2.9.12 I2S2 in master/slave mode and USART3 in synchronous mode . . . . . . 21
