February 2021 RM0351 Rev 8 1/1904

RM0351

Reference manual

STM32L47xxx, STM32L48xxx, STM32L49xxx and STM32L4Axxx

advanced Arm®-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32L47xxx/STM32L48xxx/STM32L49xxx/STM32L4Axxx microcontroller

memory and peripherals.

The STM32L47xxx/STM32L48xxx/STM32L49xxx/STM32L4Axxx is a family of

microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

corresponding datasheets.

For information on the Arm® Cortex®-M4 core, please refer to the Cortex®-M4 Technical

Reference Manual.

The STM32L47x/L48x/L49x/L4Ax microprocessors include ST state-of-the-art patented

technology.

Related documents

•Cortex®-M4 Technical Reference Manual, available from: http://infocenter.arm.com

•STM32L471xx, STM32L475xx, STM32L476xx, STM32L486xx, STM32L496xx and

STM32L4A6xx datasheets

•STM32 Cortex®-M4 MCUs and MPUs programming manual (PM0214)

In this document, the following short names, or combinations of them, may be used to refer

to subsets of the above-listed part numbers:

•STM32L47x, STM32L48x, STM32L49x, STM32L4Ax

•STM32L471, STM32L4x5, STM32L4x6

www.st.com

Contents RM0351

2/1904 RM0351 Rev 8

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.1.1 S0: I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2.1.2 S1: D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2.1.3 S2: S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2.1.4 S3, S4: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2.1.5 S5: DMA2D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2.1.6 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 76

2.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.4.1 SRAM2 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.4.2 SRAM2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

2.4.3 SRAM2 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

2.4.4 SRAM2 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

2.5 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

2.6 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

2.6.1 Boot configuration for STM32L47x/L48x devices . . . . . . . . . . . . . . . . . 91

2.6.2 Boot configuration for STM32L49x/L4Ax devices . . . . . . . . . . . . . . . . . 93

3 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.3.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96