May 2017 DocID025262 Rev 4 1/29

STM32F401xB/C

Errata sheet

STM32F401xB and STM32F401xC device limitations

Silicon identification

This errata sheet applies to STM32F401xB/C microcontrollers.

The STM32F401xB/C devices feature an ARM®32-bit Cortex®-M4 core with FPU, for which

an errata notice is also available (see Section 1 for details).

The full list of part numbers is shown in Table 2. The products are identifiable as shown in

Table 1:

•by the revision code marked below the order code on the device package

•by the last three digits of the Internal order code printed on the box label

Table 1. Device identification(1)

1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the RM0368

STM32F401xx reference manual for details on how to find the revision code).

Order code Revision code marked on device(2)

2. Refer to datasheet for the device marking.

STM32F401xB, STM32F401xC “A”, “Z”

Table 2. Device summary

Reference Part number

STM32F401xB STM32F401VB, STM32F401RB, STM32F401CB

STM32F401xC STM32F401VC, STM32F401RC, STM32F401CC

www.st.com

Contents STM32F401xB/C

2/29 DocID025262 Rev 4

Contents

1 ARM®32-bit Cortex®-M4 with FPU limitations . . . . . . . . . . . . . . . . . . . . 6

1.1 Cortex®-M4 interrupted loads to stack pointer can cause

erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 VDIV or VSQRT instructions might not complete correctly

when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 STM32F401xB/C silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.1 Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . 10

2.1.2 Debugging Stop mode with WFE entry . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.3 Wakeup sequence from Standby mode when using more than

one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.4 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 11

2.1.5 MPU attribute to RTC and IWDG registers could be managed

incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.6 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 11

2.1.7 PB5 I/O VIN limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.8 PA0 I/O VIN limitation in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.9 PH1 cannot be used as a GPIO in HSE bypass mode . . . . . . . . . . . . . 12

2.2 IWDG peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.1 RVU and PVU flags are not reset in Stop mode . . . . . . . . . . . . . . . . . . 13

2.3 RTC limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.1 Spurious tamper detection when disabling the tamper channel . . . . . . . 14

2.3.2 Detection of a tamper event occurring before enabling the tamper

detection is not supported in edge detection mode . . . . . . . . . . . . . . . . 14

2.3.3 RTC calendar registers are not locked properly . . . . . . . . . . . . . . . . . . 14

2.4 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.1 SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.2 Start cannot be generated after a misplaced Stop . . . . . . . . . . . . . . . . . 15

2.4.3 Mismatch on the “Setup time for a repeated Start condition” timing

parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.4 Data valid time (tVD;DAT) violated without the OVR flag being set . . . . . 16

2.4.5 Both SDA and SCL maximum rise time (tr) violated when VDD_I2C bus

higher than ((VDD+0.3) / 0.7) V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.6 Spurious Bus Error detection in Master mode . . . . . . . . . . . . . . . . . . . . 17