March 2020 PM0214 Rev 10 1/262
1
PM0214
Programming manual
STM32 Cortex®-M4 MCUs and MPUs programming manual
Introduction
This programming manual provides information for application and system-level software
developers. It gives a full description of the STM32 Cortex®-M4 processor programming
model, instruction set and core peripherals. The applicable products are listed in the table
below.
The Cortex®-M4 processor used in STM32F3 Series, STM32F4 Series, STM32G4 Series,
STM32H745/755 and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series,
STM32WB Series, STM32WL Series and STM32MP1 Series, is a high performance 32-bit
processor designed for the microcontroller and microprocessor market. It offers significant
benefits to developers, including:
•Outstanding processing performance combined with fast interrupt handling
•Enhanced system debug with extensive breakpoint and trace capabilities
•Efficient processor core, system and memories
•Ultra-low power consumption with integrated sleep modes
•Platform security
Reference documents
Available from STMicroelectronics web site www.st.com:
•Datasheets of STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H745/755
and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series, STM32MP1 Series,
STM32WB Series and STM32WL Series
•Reference manuals of STM32F3 Series, STM32F4 Series, STM32G4 Series,
STM32H745/755 and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series,
STM32MP1 Series, STM32WB Series and STM32WL Series
Table 1. Applicable products
Type Product Series and Lines
Microcontrollers
STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32L4 Series,
STM32L4+ Series, STM32WB Series, STM32WL Series
STM32H745/755 and STM32H747/757 Lines
Microprocessors STM32MP1 Series
www.st.com
Contents PM0214
2/262 PM0214 Rev 10
Contents
1 About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Typographical conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 About the STM32 Cortex-M4 processor and core peripherals . . . . . . . . . 13
1.3.1 System level interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.2 Integrated configurable debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.3 Cortex-M4 processor features and benefits summary . . . . . . . . . . . . . . 15
1.3.4 Cortex-M4 core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 The Cortex-M4 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 Programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.1 Processor mode and privilege levels for software execution . . . . . . . . . 17
2.1.2 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.3 Core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.4 Exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1.5 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1.6 The Cortex microcontroller software interface standard (CMSIS) . . . . . 26
2.2 Memory model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.1 Memory regions, types and attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2 Memory system ordering of memory accesses . . . . . . . . . . . . . . . . . . . 29
2.2.3 Behavior of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.4 Software ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.5 Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.6 Memory endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.7 Synchronization primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.8 Programming hints for the synchronization primitives . . . . . . . . . . . . . . 36
2.3 Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.1 Exception states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.2 Exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.3 Exception handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3.4 Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3.5 Exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.6 Interrupt priority grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.7 Exception entry and return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
