July 2019 ES0290 Rev 7 1/28

STM32F74xxx STM32F75xxx

Errata sheet

STM32F74xxx and STM32F75xxx device limitations

Applicability

This document applies to the part numbers of STM32F74xxx and STM32F75xxx devices

listed in Table 1 and their variants shown in Table 2.

Section 1 gives a summary and Section 2 a description of / workaround for device

limitations, with respect to the device datasheet and reference manual RM0385.

Table 1. Device summary

Reference Part numbers

STM32F74xxx

STM32F745ZG, STM32F745IG, STM32F745ZE, STM32F745IE,

STM32F745VG, STM32F745VE, STM32F746VG, STM32F746ZG,

STM32F746IG, STM32F746BG, STM32F746NG, STM32F746IE,

STM32F746VE, STM32F746ZE, STM32F746BE, STM32F746NE

STM32F75xxx

STM32F756VG, STM32F756ZG, STM32F756IG, STM32F756BG,

STM32F756NG

STM32F750V8, STM32F750Z8, STM32F750N8

Table 2. Device variants

Reference

Silicon revision codes

Device marking(1)

1. Refer to the device data sheet for how to identify this code on different types of package.

REV_ID(2)

2. REV_ID[15:0] bit field of DBGMCU_IDCODE register. Refer to the reference manual.

STM32F74xxx

Z and 1 0x1001

STM32F75xxx

www.st.com

Contents STM32F74xxx STM32F75xxx

2/28 ES0290 Rev 7

Contents

1 Summary of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Description of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Arm®32-bit Cortex®-M7 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.1 Cortex®-M7 data corruption when using data cache configured in

write-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.1 Missed ADC triggers from TIM1/TIM8, TIM2/TIM5/TIM4/TIM6/TRGO or

TGRO2 event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.2 Internal noise impacting the ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.3 Wakeup from Standby mode when the back-up SRAM regulator

is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.4 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . . 9

2.3 FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3.1 Dummy read cycles inserted when reading synchronous memories . . . . 9

2.3.2 Wrong data read from a busy NAND memory . . . . . . . . . . . . . . . . . . . . . 9

2.3.3 Spurious clock stoppage with continuous clock feature enabled . . . . . . 10

2.3.4 Data read might be corrupted when the write FIFO is disabled . . . . . . . 10

2.4 QUADSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.4.1 Extra data written in the FIFO at the end of a read transfer . . . . . . . . . 11

2.4.2 First nibble of data not written after a dummy phase . . . . . . . . . . . . . . . 11

2.4.3 Wrong data from memory-mapped read after an indirect mode

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.4 Memory-mapped read operations may fail when timeout counter is

enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5.1 ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 12

2.6 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6.1 DMA underrun flag management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6.2 DMA request not automatically cleared by clearing DMAEN . . . . . . . . . 13

2.7 LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7.1 MCU may remain stuck in LPTIM interrupt when entering Stop mode . 14

2.8 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.8.1 RTC calendar registers are not locked properly . . . . . . . . . . . . . . . . . . 14

2.8.2 Spurious tamper detection when disabling the tamper channel . . . . . . . 15