Applicability
This document applies to the part numbers of STM32G471xx/473xx/474xx/483xx/484xx devices and the device variants as
stated in this page.
It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0440.
Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the
description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation
erratum. The term “errata” applies both to limitations and documentation errata.
Table 1. Device summary
Reference Part numbers
STM32G471xx STM32G471CC, STM32G471CE, STM32G471ME, STM32G471QC, STM32G471QE, STM32G471RB,
STM32G471RC, STM32G471RE, STM32G471VC, STM32G471VE
STM32G473xx
STM32G473CB, STM32G473CC, STM32G473CE, STM32G473MB, STM32G473MC, STM32G473ME,
STM32G473PB, STM32G473PC, STM32G473PE, STM32G473QB, STM32G473QC, STM32G473QE,
STM32G473RB, STM32G473RC, STM32G473RE, STM32G473VB, STM32G473VC, STM32G473VE
STM32G474xx
STM32G474CB, STM32G474CC, STM32G474CE, STM32G474MB, STM32G474MC, STM32G474ME,
STM32G474PB, STM32G474PC, STM32G474PE, STM32G474QB, STM32G474QC, STM32G474QE,
STM32G474RB, STM32G474RC, STM32G474RE, STM32G474VB, STM32G474VC, STM32G474VE
STM32G483xx STM32G483CE, STM32G483ME, STM32G483PE, STM32G483QE, STM32G483RE, STM32G483VE
STM32G484xx STM32G484CE, STM32G484ME, STM32G484PE, STM32G484QE, STM32G484RE, STM32G484VE
Table 2. Device variants
Reference
Silicon revision codes
Device marking(1) REV_ID(2)
STM32G471xx/473xx/474xx/483xx/484xx Z 0x2001
STM32G471xx/473xx/474xx/483xx/484xx Y 0x2002
STM32G471xx/473xx/474xx/483xx/484xx X 0x2003
1. Refer to the device datasheet for how to identify this code on different types of package.
2. REV_ID[15:0] bitfield of DBGMCU_IDCODE register.
STM32G471xx/473xx/474xx/483xx/484xx device errata
STM32G471xx/473xx/474xx/483xx/484xx
Errata sheet
ES0430 - Rev 7 - April 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1Summary of device errata
The following table gives a quick reference to the STM32G471xx/473xx/474xx/483xx/484xx device limitations and
their status:
A = workaround available
N = no workaround available
P = partial workaround available
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
Function Section Limitation
Status
Rev.
Z
Rev.
Y
Rev.
X
Core
2.1.1 Interrupted loads to SP can cause erroneous behavior A A A
2.1.2 VDIV or VSQRT instructions might not complete correctly when very
short ISRs are used A A A
2.1.3 Store immediate overlapping exception return operation might vector
to incorrect interrupt A A A
System
2.2.1 Full JTAG configuration without NJTRST pin cannot be used A A A
2.2.2 Data cache might be corrupted during Flash memory read-while-write
operation A A A
2.2.3 FLASH_ECCR corrupted upon reset or power-down occurring during
Flash memory program or erase operation A A A
2.2.4 Unstable LSI when it clocks RTC or CSS on LSE P P P
DMA 2.3.1 DMA disable failure and error flag omission upon simultaneous
transfer error and global flag clear A A A
DMAMUX
2.4.1 SOFx not asserted when writing into DMAMUX_CFR register N N N
2.4.2 OFx not asserted for trigger event coinciding with last DMAMUX
request N N N
2.4.3 OFx not asserted when writing into DMAMUX_RGCFR register N N N
2.4.4 Wrong input DMA request routed upon specific DMAMUX_CxCR
register write coinciding with synchronization event A A A
FMC
2.5.1 Dummy read cycles inserted when reading synchronous memories N N N
2.5.2 Wrong data read from a busy NAND memory A A A
2.5.3 Data corruption upon a specific FIFO write sequence to synchronous
PSRAM A A A
QUADSPI
2.6.1 QUADSPI cannot be used in indirect read mode when only data
phase is activated P P P
2.6.2 QUADSPI hangs when QUADSPI_CCR is cleared P P P
2.6.3 QUADSPI internal timing criticality A A A
2.6.4 Memory-mapped read of last memory byte fails P P P
ADC 2.7.1 New context conversion initiated without waiting for trigger when
writing new context in ADC_JSQR with JQDIS = 0 and JQM = 0 A A A
STM32G471xx/473xx/474xx/483xx/484xx
Summary of device errata
ES0430 - Rev 7 page 2/34
