June 2016 DocID022648 Rev 3 1/38

AN4031

Application note

Using the STM32F2, STM32F4 and STM32F7 Series

DMA controller

Introduction

This application note describes how to use direct memory access (DMA) controller available

in STM32F2, STM32F4 and STM32F7 Series. The DMA controller features, the system

architecture, the multi-layer bus matrix and the memory system contribute to provide a high

data bandwidth and to develop very low latency response-time software.

This application note also describes some tips and tricks to allow developers to take full

advantage of these features and ensure correct response times for different peripherals and

subsystems.

STM32F2, STM32F4 and STM32F7 are referred to as “STM32F2/F4/F7 devices” and the

DMA controller as “DMA” throughout the document.

In this document STM32F4 Series is selected as illustrative example. DMA behavior is the

same over STM32F2, STM32F4 and STM32F7 Series unless otherwise specified.

Reference documents

This application note should be read in conjunction with the STM32F2/F4/F7 reference

manuals:

•STM32F205/215 and STM32F207/217 reference manual (RM0033)

•STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439 reference

manual (RM0090)

•STM32F401xB/C and STM32F401xD/E reference manual (RM0368)

•STM32F410 reference manual (RM0401)

•STM32F411xC/E reference manual (RM0383)

•STM32F412 reference manual (RM0402)

•STM32F446xx reference manual (RM0390)

•STM32F469xx and STM32F479xx reference manual (RM0386)

•STM32F75xxx and STM32F74xxx reference manual (RM0385)

•STM32F76xxx and STM32F77xxx reference manual (RM0410)

www.st.com

Contents AN4031

2/38 DocID022648 Rev 3

Contents

1 DMA controller description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 DMA transfer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.1 DMA streams/channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.2 Stream priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1.3 Source and destination addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1.4 Transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1.5 Transfer size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1.6 Incrementing source/destination address . . . . . . . . . . . . . . . . . . . . . . . 10

1.1.7 Source and destination data width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1.8 Transfer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1.9 DMA FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1.10 Source and destination burst size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.1.11 Double-buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.1.12 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.2 Setting up a DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 System performance considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 Multi-layer bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.2 Round-robin priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1.3 BusMatrix arbitration and DMA transfer delays worst case . . . . . . . . . . 19

2.2 DMA transfer paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.1 Dual DMA port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.2 DMA transfer states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.2.3 DMA request arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3 AHB-to-APB bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.3.1 Dual AHB-to-APB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.3.2 AHB-to-APB bridge arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3 How to predict DMA latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 DMA transfer time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.1 Default DMA transfer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.2 DMA transfer time versus concurrent access . . . . . . . . . . . . . . . . . . . . 27

3.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28