June 2018 ES0321 Rev 6 1/36
1
STM32F469xx and STM32F479xx
Errata sheet
STM32F469xx and STM32F479xx line limitations
Applicability
This document applies to the part numbers of STM32F469xx and STM32F479xx devices
listed in Table 1, and to their variants, shown in Table 2.
Section 1 gives a summary and Section 2 a description of workarounds for device
limitations, with respect to the device datasheet and reference manual RM0386.
Table 1. Device summary
Reference Part numbers
STM32F469xx
STM32F469AE, STM32F469AG, STM32F469AI
STM32F469BE, STM32F469BG, STM32F469BI
STM32F469IE, STM32F469IG, STM32F469II
STM32F469NE, STM32F469NG, STM32F469NI
STM32F469VE, STM32F469VG, STM32F469VI
STM32F469ZE, STM32F469ZG, STM32F469ZI
STM32F479xx
STM32F479AI, STM32F479AG
STM32F479BI, STM32F479BG
STM32F479II, STM32F479IG
STM32F479NI, STM32F479NG
STM32F479VI, STM32F479VG
STM32F479ZI, STM32F479ZG
Table 2. Device variants
Reference
Silicon revision codes
Device marking(1)
1. Refer to the device datasheet for details on how to identify this code on different types of package.
REV_ID(2)
2. The REV_ID[15:0] bit field of DBGMCU_IDC register (refer to the reference manual RM0386).
STM32F469xx, STM32F479xx “A”, “1” 0x1000
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Contents STM32F469xx and STM32F479xx
2/36 ES0321 Rev 6
Contents
1 Summary of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Interrupted loads to stack pointer can cause erroneous behavior . . . . . . 9
2.1.2 VDIV or VSQRT instructions might not complete correctly
when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Store immediate overlapping exception return operation
might vector to incorrect interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Debugging Sleep/Stop mode with WFE/WFI entry . . . . . . . . . . . . . . . . 12
2.2.3 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 13
2.2.4 MPU attribute to RTC and IWDG registers could be managed
incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.5 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 13
2.2.6 Internal noise impacting the ADC accuracy . . . . . . . . . . . . . . . . . . . . . . 14
2.2.7 Wakeup from Standby mode with RTC . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.8 Data Cache might be corrupted during Flash Read While Write
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.9 FMC_SDNWEN alternate function on PA7 . . . . . . . . . . . . . . . . . . . . . . 15
2.3 FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Dummy read cycles inserted when reading synchronous memories . . . 16
2.4 QUADSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 Extra data written in the FIFO at the end of a read transfer . . . . . . . . . 16
2.4.2 First nibble of data is not written after dummy phase . . . . . . . . . . . . . . 16
2.4.3 Wrong data can be read in memory-mapped after an indirect
mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.4 Memory-mapped read operations may fail when timeout counter
is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5.1 ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 18
2.6 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.1 DMA underrun flag management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.2 DMA request not automatically cleared by DMAEN=0 . . . . . . . . . . . . . 18
